1. Field of the Disclosure
The present disclosure relates to electronic circuits.
2. Description of the Related Art
In general, a power-on reset is used to initialize a digital circuit in an electronic device when it is powered on. In the power-on reset, for example, when the electronic device is powered on, the electronic device is initialized by supplying a reset signal to the digital circuit with a delay from the time when it is powered on.
FIG. 3 shows a circuit diagram which indicates an example of an electronic circuit in which a digital circuit is asynchronously reset by a power-on reset. FIG. 4 shows a timing chart which indicates an example of a clock signal, a power-on reset signal, and a status of an output terminal in the electronic circuit shown in FIG. 3.
In the electronic circuit shown in FIG. 3, a clock generator circuit 2 and a power-on reset circuit 3 are connected to an IC (Integrated Circuit) chip 101. A clock signal CLK is inputted from the clock generator circuit 2 to a CLK terminal of the IC chip 101, and a power-on reset signal POR is inputted from the power-on reset circuit 3 to a POR terminal of the IC chip 101.
The IC chip 101 includes a digital circuit 111, and an output signal of the digital circuit 111 is applied to an output terminal TAR via an output buffer 112.
In a noiseful environment, if this power-on reset signal is directly used as a reset signal for an asynchronous reset, the digital circuit 111 is reset by noise in error. Therefore, a noise eliminating circuit 113 eliminates noise in the power-on reset signal.
Into the noise eliminating circuit 113, the clock signal CLK is supplied via an input buffer 114, and the power-on reset signal POR is supplied via an input buffer 115; and an output signal thereof in which noise has been eliminated (a reset signal RST) is used for an asynchronous reset of the digital circuit 111. The noise eliminating circuit 113 delays the power-on reset signal by a predetermined number of clocks, eliminates noise in the power-on reset signal by performing a logical operation between the delayed power-on reset signal and the current power-on reset signal, and outputs a signal obtained by the logical operation as the reset signal RST. Therefore, even if noise occurs in the power-on reset signal, the digital circuit 111 is not reset due to the noise.
However, in the case that the digital circuit 111 is initialized in such way, a delay period until a reset status due to the power-on reset signal is released and the reset signal RST is supplied to the digital circuit 111 (i.e. a period from the power-on timing To to the time T1 in FIG. 4) must be set longer than the delay at the noise eliminating circuit 113, and consequently, during the delay period, the value of the output signal of the digital circuit is invalid (i.e. indefinite). Therefore, during this period, a circuit or device connected to the output terminal TAR may malfunction.
For instance, in the case that a control signal for a motor is outputted from the output terminal TAR, upon a power-on, during the period when the value of the output signal of the digital circuit 111 is invalid (i.e. indefinite), the control signal may take an unexpected value and the motor runs unexpectedly.